Hog Local

• Project configuration file
  • Telling Hog the IDE tool to be used
    • Why do wee need the tool version?
  • Main section: project variables
    • PART
    • FAMILY
  • Synthesis and implementation sections (Xilinx only)
  • Parameters section (Xilinx only)
  • Hog section
  • Generics section
  • XSA Export for Zynq Devices (Xilinx Only)
• List Files
  • Source list files (.src)
    • Intel Platform Designer systems
  • Simulation list files (.sim)
  • Constraint list files (.con)
  • List files are recursive
  • External list files (.ext)
• Hog buttons
  • Adding the buttons to the GUI
  • Button functionalities
    • The check button
    • The list button
    • The configuration button
• Simulation
  • Simulation sets
  • Simulation Configuration File
    • Generics section
  • Project simulator
    • Simulation Library
  • Simulation in the CI
  • Simulating without GUI
• Parameters/Generics
• Usage (Hog/Do Script)
  • Directives
  • Command Options
  • Usage Examples
    • Create a project
    • Creating a Project and Launching Workflow
    • Simulating a Project (Vivado-only)
    • Running Synthesis Only
    • Listing Projects
    • Displaying Help
  • Running the workflow using Vivado/Quartus GUI
  • Collecting workflow products
  • Simulating with Vivado GUI
• Custom User Tcl scripts in build flow
  • User Tcl scripts at project-creation time
  • User Tcl scripts during the workflow
• Templates
  • hog.conf
  • top.vhd
  • top.v
  • gitlab-ci.yml
  • gitlab-ci_dynamic.yml
  • gitlab-ci_parallel.yml
  • ci.conf
  • gitignore
  • doxygen.conf
• Hog flavour
  • What is Hog’s flavour?
  • Possible use cases
• Additional Tcl Scripts
  • check_syntax.tcl
  • check_list_files.tcl
  • add_hog_custom_button.tcl
  • compile_modelsimlib.tcl (VIVADO ONLY)
  • compile_questalib.tcl (VIVADO ONLY)
  • compile_riviera.tcl (VIVADO ONLY)
  • get_ips.tcl (VIVADO ONLY)
  • make_doxygen.tcl
  • check_yaml_ref.tcl
  • copy_xml.tcl
  • project_sha.tcl
  • generate_yaml.tcl
  • reformat.tcl
• Hog and IPbus
  • Embedding of version and SHA in the XML files
  • xml.lst
    • IPbus xml files
  • Check address maps against xml file
  • Generation of VHDL address maps
• List of supported tools
• Hog and Sigasi
• Intellectual Properties (IP)
  • Keep the IP locked (Vivado only)
  • XCIX (IP Core Containers)
    • IP initialisation files (.coe, .mif)
  • Creating the IPs/BDs with a Tcl script (Hog > 2022.1, Vivado Only)
  • Speed up the IP synthesis (Optional)
• User IPs
• Using Hog with Libero SoC
  • Tcllib
  • Libero IP Cores
  • CI requirements
  • Simulations
• Coloured Output Logs
  • Coloured output
  • Save Logs