# Glossary Key terms used throughout the Hog documentation. --- **Bitstream** The binary file produced at the end of the FPGA build flow (synthesis + implementation). It is programmed onto the FPGA device to configure its logic. Hog embeds the project version and git SHA into the bitstream so that every binary file is traceable back to its exact source code. --- **Block Design (BD)** A Vivado-specific visual design entry method where logic blocks are connected graphically. The design is stored as a `.bd` file, which should be committed to the repository and added to a `.src` list file. --- **Describe string** A human-readable string that uniquely identifies the state of a project, combining the version tag, the number of commits since that tag, the short git SHA, and a `dirty` suffix if the repository had uncommitted changes at build time. Example: `1.2.3-5-gabcdef0-dirty`. Retrieved with `./Hog/Do VERSION -describe`. --- **Dirty repository** A repository that has uncommitted local changes. Hog detects a dirty state at synthesis time and issues a Critical Warning, setting the version to `0.0.0`. This guarantees that only clean, committed states produce valid version numbers. --- **`hog.conf`** The project configuration file, located at `Top//hog.conf`. It tells Hog which FPGA device to target, which synthesis and implementation strategies to use, how many parallel jobs to run, and optionally defines generics to pass to the top-level HDL module. A template is available at `Hog/Templates/hog_vivado.conf`. See [hog.conf reference](../02-User-Manual/01-Hog-local/01-conf.md). --- **Hog buttons** Custom buttons added to the Vivado GUI toolbar by Hog. They allow Vivado users to check and update Hog list files directly from within the IDE, without leaving Vivado. See [Hog Buttons](../02-User-Manual/01-Hog-local/02a-Hog-Buttons.md). --- **Hog submodule** The Hog scripts are included in every Hog-managed repository as a git submodule at `Hog/`. This means Hog itself is version-controlled alongside your design. When cloning, use `git clone --recursive` to ensure the submodule is fetched. --- **Implementation** The place-and-route step of the FPGA build flow, which follows synthesis. It maps the netlist produced by synthesis onto the physical resources of the target FPGA device. Run with `./Hog/Do IMPLEMENTATION `. --- **IP (Intellectual Property core)** A pre-built, reusable design block provided by the IDE vendor or a third party. In Vivado, IPs are represented by `.xci` files. These files should be committed to the repository and listed in a `.src` or `.ext` list file. --- **Library** In Hog, a library is a named group of HDL source files. Each `.src` list file defines one library: the library name is the filename without the `.src` extension (e.g., `mylib.src` defines library `mylib`). This library name must match the HDL library declaration in your VHDL or Verilog files, and in Vivado it corresponds to the compile library set in the Sources panel. --- **List file** A plain-text file in `Top//list/` that lists the source files belonging to a Hog project, one path per line (relative to the repository root). Hog reads these files to populate the IDE project. See [List Files](../02-User-Manual/01-Hog-local/02-List-files.md) for full details. --- **Project top-directory** The per-project subdirectory inside `Top/`, named after the project (e.g., `Top/myproject/`). It contains the `hog.conf` configuration file and the `list/` subdirectory with all list files. --- **Reproducibility** The guarantee that building the same committed state of the repository produces an identical binary. Hog enforces this by requiring all source files to be committed to git before synthesis. --- **Simulation set** A named group of simulation source files, defined by a `.sim` list file. Hog creates one IDE simulation set per `.sim` file. Run a specific set with `./Hog/Do SIMULATION -simset `. See [Simulation](../02-User-Manual/01-Hog-local/02b-Simulation.md). --- **Synthesis** The first step of the FPGA build flow, which translates HDL source code into a technology-mapped netlist for the target device. Run with `./Hog/Do SYNTH `. --- **Top directory** The `Top/` folder at the root of the repository. It contains one subdirectory per Hog project. The name of each subdirectory becomes the project name used in all `Hog/Do` commands. --- **Top module** The highest-level HDL entity or module in the design hierarchy — the one that gets synthesised and implemented. It is usually specified in `hog.conf` under the `[main]` section as `top_module`. --- **Traceability** The ability to identify exactly which source code revision produced a given binary file. Hog embeds the git SHA and version into the bitstream at synthesis time, so any binary can be matched back to its exact repository state. --- **Version** A semantic version string (e.g., `1.2.3`) derived from the most recent git tag on the current branch. Hog reads this automatically at synthesis time and embeds it in the binary. Retrieve it with `./Hog/Do VERSION `. --- **Workflow** The full FPGA build sequence: synthesis → implementation → bitstream generation. Run the complete workflow with `./Hog/Do WORKFLOW `. Individual steps can also be run separately with `SYNTH`, `IMPLEMENTATION`, and `WORKFLOW -bitstream_only`.