Parameters/Generics

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Outdated Documentation! This documentation version is out of date. Please check the latest version 2026.1.

At project creation time and just before synthesis starts[1][2], Hog injects a set of values into your design.

This mechanism links the generated binary file to the exact state of the repository at the moment of synthesis. Hog achieves this by leveraging VHDL generics or Verilog parameters[3]. This section details the generics/parameters provided by Hog.

These generics/parameters should be connected to dedicated registers that can be accessed at run time on the device (e.g., via IPBus/AXI registers).

To access the Hog generics/parameters, you must define the following in your top-level entity:

Name	Type (VHDL)	Size	Description
GLOBAL_DATE	std_logic_vector	32 bit	Date of last commit when the project was modified. Format: ddmmyyyy (hex with decimal digits, no digit greater than 9 is used)
GLOBAL_TIME	std_logic_vector	32 bit	Time of last commit when the project was modified. Format: 00HHMMSS (hex with decimal digits, no digit greater than 9 is used)
GLOBAL_VER	std_logic_vector	32 bit	Last version tag when the project was modified. Version m.M.p encoded as 0xMMmmpppp
GLOBAL_SHA	std_logic_vector	32 bit	Git commit hash (SHA) of the last commit when the project was modified
TOP_VER	std_logic_vector	32 bit	Version of the top directory (containing hog.conf and other files), encoded as 0xMMmmpppp
TOP_SHA	std_logic_vector	32 bit	Git commit hash (SHA) of the top directory
CON_VER	std_logic_vector	32 bit	Version of the constraint files, encoded as 0xMMmmpppp
CON_SHA	std_logic_vector	32 bit	Git commit hash (SHA) of the constraint files
HOG_VER	std_logic_vector	32 bit	Hog submodule version, encoded as 0xMMmmpppp
HOG_SHA	std_logic_vector	32 bit	Hog submodule git commit hash (SHA)
XML_VER	std_logic_vector	32 bit	(optional) IPbus XML version, encoded as 0xMMmmpppp
XML_SHA	std_logic_vector	32 bit	(optional) IPbus XML git commit hash (SHA)
<MYLIB>_VER	std_logic_vector	32 bit	(one per library, i.e., per .src list file) Version of the files in the .src file, encoded as 0xMMmmpppp
<MYLIB>_SHA	std_logic_vector	32 bit	(one per library, i.e., per .src list file) Git commit hash of the files in the .src file
<MYEXTLIB>_SHA	std_logic_vector	32 bit	(one per external library) Git commit hash (SHA) of the .ext file
FLAVOUR	integer		(integer) Flavour used for generating this bit file, set if your project uses Hog flavours to produce bit files for different devices

Encoding details:

• Dates and times are encoded in hexadecimal using only decimal digits (0–9). For example, the date 5 July 1952 is encoded as 0x05071952, and the time 12:34:56 as 0x00123456.

• Version numbers of the form M.m.p are encoded as 0xMMmmpppp. For example, version 7.10.255 becomes 0x070A00FF.

• SHA values are the 7-digit hexadecimal git commit hash.

To guarantee synthesis reproducibility, Hog uses the last-commit date and time, not the synthesis date and time.

The version and hash for a subset of files are calculated using git log, meaning the latest commit (and version tag) where at least one of those files was changed. Note that there is not a one-to-one correspondence between tag and hash, as not all commits are tagged—a tag can correspond to several hashes (all those between that tag and the previous one).

You are not required to use all these generics/parameters in your design. If you do not need them, you can leave them unconnected or omit them from your top module; the HDL synthesizer will ignore them (though it may issue a warning)[4].

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[1]

Under Quartus, the script is run as a PRE-FLOW script. This means you must launch the full compilation flow to assign default values to the generics. Running single steps may cause the compilation to fail.

[2]

Unlike Vivado, PlanAhead/ISE does not support built-in pre-synthesis scripts. In this case, Hog’s pre-synthesis, pre-implementation, and pre/post-bitstream scripts are run by the Hog tool itself, so assignment of generics and other Hog build features only happen when using Hog from the command line or from CI. Builds made in the GUI will not have the Hog generics populated.

[3]

Generics are used in VHDL; parameters are used in Verilog

[4]

ISE/PlanAhead handles this somewhat problematically: assignment of a non-existent generic in PlanAhead creates an HDL compiler error. To use Hog with PlanAhead, ensure all Hog generics are exposed in the top-level design for synthesis.