Design Hierarchy

Warning

This feature is still experimental and may not work as expected in all scenarios. Please report any issues you encounter to the Hog development team.

Using the TREE command, Hog can generate a design hierarchy diagram of your project. This diagram can help you visualize the structure of your design, including the relationships between different modules and components.

To generate a design hierarchy diagram for a Hog-managed project, run the following command in your terminal:

./Hog/Do TREE <project_name> [options]

Replace <project_name> with the name of your project. You can also specify additional options to customize the output:

Options:

• compile_order — Print the compilation order instead of the hierarchy.

• ext_path <path> — Absolute path for external libraries.

• ignore <pattern> — Ignore modules matching the given pattern.

• include_gen_prods — Include IP generated products in the hierarchy.

• include_ieee — Include IEEE and STD library components in the hierarchy.

• light — Print a simplified hierarchy (without file paths).

• output <file> — Write the hierarchy into the specified file.

• top <module> — Specify a different top module for the hierarchy.

• verbose — Enable verbose output.

The generated hierarchy diagram will be printed to the console by default. If you specify the output option, the diagram will be saved to the specified file instead.

Example

(base) ➜  hog-examples git:(2026.1) ✗ ./Hog/Do T Top/vivado/fifo -include_ieee
*********************************************************
*                 _  _            ___ __ ___  __   _    *
*  (\____/)      | || |___ __ _  |_  /  |_  )/ /  / |   *
*  / @__@ \      | __ / _ / _` |  / | () / // _ \_| |   *
* (  (oo)  )     |_||_\___\__, | /___\__/___\___(_|_|   *
*     ~~                  |___/                         *
*                                                       *
* Copyright 2018-2026  The University of Birmingham     *
* Documentation: https://cern.ch/hog                    *
* Register to our newsletter: http://cern.ch/go/nBn8    *
* Version: v9.77.0-2-g41ce8b68                          *
*********************************************************

INFO: [Hog:CheckLatestHogRelease] Checking for latest Hog release, can take up to 5 seconds...
INFO: [Hog:CheckLatestHogRelease] Latest official version is Hog2025.2-5, nothing to do.
INFO: [Hog:InitLauncher] Project vivado/fifo uses vivado IDE
INFO: [Hog:Hierarchy] Top module from properties: fifo.vhdl_entity.top_fifo
INFO: [Hog:Hierarchy] Completed initial parsing in 13.565 ms
INFO: [Hog:Hierarchy] Completed reference resolution: 3 references resolved in 0.712 ms

fifo.top_fifo.behavioral (vhdl_architecture) - /home/dcieri/Work/Hog/hog-examples/sources/top/top_fifo.vhd
  ├─ fifo.adder.behavioral (vhdl_architecture) - /home/dcieri/Work/Hog/hog-examples/sources/src/adder.vhd
  ├─ ips.fifo_generator_0 (component) - /home/dcieri/Work/Hog/hog-examples/IP/fifo_generator_0/fifo_generator_0.xci
  └─ other_lib.different_adder.behavioral (vhdl_architecture) - /home/dcieri/Work/Hog/hog-examples/sources/src/different_adder.vhd


=====Packages in project:=====
Library: ieee
  Package: std_logic_1164
  Package: numeric_std

To print the compilation order instead of the hierarchy, use the compile_order option:

(base) ➜  hog-examples git:(2026.1) ✗ ./Hog/Do T Top/vivado/fifo -compile_order
*********************************************************
*                 _  _            ___ __ ___  __   _    *
*  (\____/)      | || |___ __ _  |_  /  |_  )/ /  / |   *
*  / @__@ \      | __ / _ / _` |  / | () / // _ \_| |   *
* (  (oo)  )     |_||_\___\__, | /___\__/___\___(_|_|   *
*     ~~                  |___/                         *
*                                                       *
* Copyright 2018-2026  The University of Birmingham     *
* Documentation: https://cern.ch/hog                    *
* Register to our newsletter: http://cern.ch/go/nBn8    *
* Version: v9.77.0-2-g41ce8b68                          *
*********************************************************

INFO: [Hog:CheckLatestHogRelease] Checking for latest Hog release, can take up to 5 seconds...
INFO: [Hog:CheckLatestHogRelease] Latest official version is Hog2025.2-5, nothing to do.
INFO: [Hog:InitLauncher] Project vivado/fifo uses vivado IDE
INFO: [Hog:Hierarchy] Top module from properties: fifo.vhdl_entity.top_fifo
INFO: [Hog:Hierarchy] Completed initial parsing in 14.246 ms
INFO: [Hog:Hierarchy] Completed reference resolution: 3 references resolved in 0.688 ms

VHDL2008 {/home/dcieri/Work/Hog/hog-examples/sources/src/different_adder.vhd}
XCI {/home/dcieri/Work/Hog/hog-examples/IP/fifo_generator_0/fifo_generator_0.xci}
VHDL93 {/home/dcieri/Work/Hog/hog-examples/sources/src/adder.vhd}
VHDL2008 {/home/dcieri/Work/Hog/hog-examples/sources/top/top_fifo.vhd}