.md .pdf

repository open issue

Hog Local

• Project Tcl file
  • Telling Hog the HDL compiler to be used
  • TCL Variables
    • FPGA
    • FAMILY
    • SYNTH_STRATEGY
    • SYNTH_FLOW
    • IMPL_STRATEGY
    • IMPL_FLOW
    • SIMULATOR
    • DESIGN
    • PROPERTIES
    • PATH_REPO
    • BIN_FILE
  • Running additional scripts
• List Files
  • Source list files (.src)
  • Simulation list files (.sim)
  • Constraint list files (.con)
  • List files are recursive
  • Properties list files (.prop)
  • External list files (.ext)
• Simulation
  • Simulation sets
  • Project simulator
  • Simulation in the CI
  • Simulating without GUI
• Parameters/Generics
• Creating, building and simulating projects
  • Create project
  • Using shell
    • Using Vivado/Quartus Tcl console
  • Building the HDL project
    • Workflow launcher
    • Running the workflow from a shell
  • Running the workflow using Vivado/Quartus GUI
  • Collecting workflow products
  • Run simulation
    • Using shell
    • Using Vivado GUI
• Templates
  • project_vivado.tcl
  • project_ise.tcl
  • project_quartus.tcl
  • top.vhd
  • top.v
  • gitlab-ci.yml
  • gitlab-ci_dynamic.yml
  • ci.conf
  • gitignore
  • doxygen.conf
• Hog flavour
  • What is Hog’s flavour?
  • Possible use cases
• Additional Tcl Scripts
  • check_syntax.tcl
  • check_list_files.tcl
  • add_hog_custom_button.tcl
  • compile_modelsimlib.tcl
  • compile_questalib.tcl
  • get_ips.tcl
  • make_doxygen.tcl
  • check_yaml_ref.tcl
  • copy_xml.tcl
  • project_sha.tcl
  • generate_yaml.tcl
  • reformat.tcl
• Hog and IPbus
  • Embedding of version and SHA in the xml files
  • xml.lst
    • IPbus xml files
  • Check address maps against xml file
  • Generation of VHDL address maps
• List of supported tools
• Hog git hooks
  • Merge Request description keywords
  • Commit keywords
• Hog and Sigasi
• Intellectual Properties (IP)
  • Keep the IP locked (Vivado only)
    • IP initialisation files (.coe, .mif)

Hog general overview Project Tcl file